Meeting the design challenges of nano-CMOS electronics

Tim Drysdale

Investigator

Department of Electronics and Electrical Engineering
Electromagnetics Design Group
University of Glasgow
Glasgow
G12 8LT
United Kingdom

web: http://userweb.elec.gla.ac.uk/t/tdd

Interconnects are a key factor limiting integrated circuit performance and also suffer from intrinsic parameter fluctuations due to line edge roughness. We are modelling ensembles of interconnect structures with realistic line edge roughness in order to predict interconnect variability at upcoming technology nodes.

	Meeting the design challenges of nano-CMOS Electronics UK consortium to use e-Science and Grid technology to tackle nano-CMOS design challenges
Menu Home People Publications Presentations Mailing Lists Partners Workshop Secure Site	You are here: Home » People » Tim Drysdale Tim Drysdale Investigator Department of Electronics and Electrical Engineering Electromagnetics Design Group University of Glasgow Glasgow G12 8LT United Kingdom web: http://userweb.elec.gla.ac.uk/t/tdd Interconnects are a key factor limiting integrated circuit performance and also suffer from intrinsic parameter fluctuations due to line edge roughness. We are modelling ensembles of interconnect structures with realistic line edge roughness in order to predict interconnect variability at upcoming technology nodes.

Meeting the design challenges of nano-CMOS Electronics

Tim Drysdale

Investigator