Meeting the design challenges of nano-CMOS electronics

Steve Furber

Investigator

The Advanced Processor Technologies Group
School of Computing Science
University of Manchester
Oxford Road
Manchester, M13 9PL
UK

web: http://intranet.cs.man.ac.uk/apt/people/sfurber/

My contribution to the project so far has been to consider the practical limits to fault-tolerant design from an information theoretic viewpoint. Alongside this my team has been developing a fault-tolerant massively-parallel architecture for spiking neural modelling, and we plan to use this design (or parts of it, depending on practical limitations) as a vehicle for the analysis of the effects of variability using the models, tools and techniques developed by our partners in this project.

	Meeting the design challenges of nano-CMOS Electronics UK consortium to use e-Science and Grid technology to tackle nano-CMOS design challenges
Menu Home People Publications Presentations Mailing Lists Partners Workshop Secure Site	You are here: Home » People » Steve Furber Steve Furber Investigator The Advanced Processor Technologies Group School of Computing Science University of Manchester Oxford Road Manchester, M13 9PL UK web: http://intranet.cs.man.ac.uk/apt/people/sfurber/ My contribution to the project so far has been to consider the practical limits to fault-tolerant design from an information theoretic viewpoint. Alongside this my team has been developing a fault-tolerant massively-parallel architecture for spiking neural modelling, and we plan to use this design (or parts of it, depending on practical limitations) as a vehicle for the analysis of the effects of variability using the models, tools and techniques developed by our partners in this project.

Meeting the design challenges of nano-CMOS Electronics

Steve Furber

Investigator