Meeting the design challenges of nano-CMOS Electronics

Sonia Paluchowski

Research Assistant

Department of Electronics and Electrical Engineering
University of Glasgow
Rankine Building
Oakfield Avenue
Glasgow G12 8LT
United Kingdom


web: http://www.gla.ac.uk/departments/electronicsandelectricalengineering/ourstaff/researcherhomepages/soniahpaluchowski/#d.en.38535

In this project my focus is on investigating the effects of device variability, in 35/25/18/13nm gate length devices, on digital circuit performance. This includes developing methodologies to reduce the adverse effects of variability on circuits. This involves working with existing design tools such as Cadence Analogue Design Environment and developing scripts and code to automate SPICE simulations of circuits. Other research interests include device modelling and digital circuit design with GaAs/Ga2O3 and SiGe devices.