1st Annual NanoCMOS Review Meeting
The 1st Annual NanoCMOS Review meeting will take place at the Royal College of Physcians in London. (see linked map for location and directions). This review meeting will outline the progress and goals of the NanoCMOS project to date. It will also seek to highlight the direction that following years of research will take. The agenda for the meeting follows below. For more information or to express an interest in attending this meeting please feel free to contact us at info@nanocmos.ac.uk
Agenda
| Time |
Title |
Speaker |
Organisation |
9.30 |
An Introduction to the NanoCMOS project
|
Asen Asenov |
University of Glasgow |
9.40 |
Simulation of Variability in nanoCMOS Devices
Abstract: Intrinsic parameter variations introduced by discreteness of charge and granularity of matter are becoming a major source of statistical variability which affects SRAM design and timing for the 45 nm technology node and will profoundly affect yield in digital circuits at 32 nm. We present the project vision for predictive simulation of statistical variability at the technology development stage. This will allow the designers to factor the expected varibility in their design before reliable measurements of the variability becomes avaliable after the technology ramp up.
|
Asen Asenov |
University of Glasgow |
10.00 |
Statistical Compact Model Strategies and Circuit Simulation
Abstract: An essential undertaking in successful variability-aware sytems design is the transfer of device intrinsic parameter fluctuations into the more abstract compact model domain. We describe the manual strategies used to perform this transfer, and the results obtained - results which clearly emphasise the future industrial importance of this work. We present the new methodologies developed during the NanoCMOS project, discuss their advantages, and present results obtained using the new tools.
|
Scott Roy |
University of Glasgow |
10.20 |
Interconnect Variability
Abstract: Interconnects are a key factor determining overall circuit performance. Analogously to intrinsic parameter fluctuations in nano-CMOS transistors, nano-scale interconnects suffer from capacitance and resistance (and hence delay) variability due to line edge roughness.
|
Tim Drysdale |
University of Glasgow |
10.40 |
Coffee |
|
|
11.00 |
Supporting EEE-Science
Abstract: The EPSRC pilot project Meeting the Design Challenges of nanoCMOS Electronics has been funded to address the challenges facing next generation nanoCMOS electronics design caused by decreasing dimensions of transistor devices and their atomistic variability. This presentation and demonstration will show how these issues are being addressed through Grid-based infrastructures based upon the OMII-UK technology dealing with key concerns of the electronics community including especially: fine grained security; simple access to a variety of HPC resources and addressing issues of large scale and heterogeneous data management.
|
Rich Sinnott, Gordon Stewart, Liangxiu Han, Gareth Roy, Campbell Millar |
Universities of Glasgow and Edinburgh |
11.30 |
Circuit Motifs and Minimising the Effect of Atomistic Variation
Abstract: The design of standard cell libraries with up to 400 cells has become increasingly arduous as tolerance spread grows. One alternative is to minimise the complexity of the basic cell to a sub gate level that we call a motif. By analysing these motifs in detail we can produce better qualified designs more easily, and potentially find ways of designing circuits that are less sensitive to the variation in device characteristics.
|
David Cumming |
University of Glasgow |
11.45 |
Building Reliable Structures from Balsa(wood?)
Abstract: Confronting the challenges of variability in the era of nanoCMOS will require a many-faceted strategy. One approach is to use self-timed techniques to cope with variable transistor performance. Asynchronous (self-timed) circuits, while possessing many appealing properties, have had a reputation as being difficult to design. Balsa is a lightweight framework for easily modelling and constructing asynchronous systems.
|
Doug Edwards |
University of Manchester |
12.00 |
Cell-Level Behavioural Modelling
Abstract: As device geometries and supply voltages both decrease, the behaviour of digital cells is becoming more analogue in nature. Traditional logic simulators cannot predict the range of variations in the functions of cells. Analogue modelling languages offer a way to capture cell behaviour more accurately than digital simulation, but with less computational cost than transistor-level modelling.
|
Mark Zwolinski |
University of Southhampton |
12.15 |
Next Generation Electronic Circuits - Nature not Nurture!
Abstract: This talk describes the basic design and early proof-of-concept results obtained from a new evolutionary software platform which is designed to create basic electronic circuits, both digital and analogue, which can be used as the building blocks for more complex circuits.
|
Andy Tyrell |
University of York |
12.30 |
Close |
Asen Asenov |
University of Glasgow |