ESSDERC/ESSCIRC Workshop
cmos variability research in europe: from atomic scale to circuits and systems

As microelectronics tends towards nanoelectronics, new materials issues affect device performance. Current transistor dimensions already fall below 40 nm and a CMOS transistor with a mere 6 nm channel length has been demonstrated. The sub 10 nm length scale creates new materials challenges for which modelling of materials, interfaces, dopants, and defects will be crucial to process design and device performance enhancement. The integrated circuit components will soon comprise tens of thousands of atoms or less, so approaching molecular scales. Therefore developing accurate and efficient theoretical tools and models is vital for defect metrology of these complex systems.

To cope with some of these issues, during the last several years the microelectronics has undergone the most significant materials revolution in 40 years by changing gate oxide from silicon oxide to a much more complex materials combination, including a stack of thin layers of oxides with a higher dielectric constant than SiO₂ (high-k oxides), e.g. HfO₂ and Hf silicates. Recent advances in film deposition techniques dramatically improved quality of hafnia films grown on silicon as well as quality of interfaces with both silicon substrate and metal gate. However, the performance of prototype high-k transistors is still affected by large concentrations of various defects. Oxygen vacancies and interstitial ions as well as grain boundaries and other defects in HfO₂ and SiO₂ films and at HfO₂/SiO₂/Si interface are often implicated in causing problems and variability in device performance.

We will discuss challenges faced by defect detection and metrology and Link between “ab initio” material simulation and variability of devices. In particular, there is an ongoing debate regarding the effect of structure of gate oxides on their properties. A generic issue for both current and future devices remains whether crystalline or amorphous oxide is more appropriate. One of the main arguments has always been that polycrystalline oxide films inevitably comprise boundaries between crystallites. Grain boundaries have been implicated in promoting leakage both in terms of ion and electron transport but there are almost no theoretical data to support that. In this presentation we will discuss and compare theoretical models of defects in amorphous silica and in “amorphized” hafnia with those at grain boundaries in HfO₂.

We will demonstrate that dislocations forming as a part of the interface between HfO₂ grains may also lead to trapping of electrons and holes in one-dimensional states. Electrons and holes may then subsequently trap at defects and impurities that segregate to grain boundaries. In contrast to low-k oxides, however, the increased flexibility of the HfO₂ lattice and higher dielectric constant encourages the formation of polarons inside the dislocation cores. Thus passivating the interfaces between grains, e.g. by SiO₂, may be essential for device reliability. We will then turn to modeling HfO₂/SiO₂/Si interfaces and predicting defect types at the interfaces and in thin SiO₂ layers. We will discuss the interface structure and the band alignment in this system, some effects of HfO₂ amorphization and electrical properties of defects located in various regions of the interface. Our results demonstrate the importance of interfaces in determining the properties of these nano-scale layered systems.