ESSDERC/ESSCIRC Workshop
cmos variability research in europe: from atomic scale to circuits and systems

CMOS transistor scaling has driven the phenomenal success of the semiconductor industry, delivering cheaper, faster, more functional circuits. However as devices scale, microscopic variations in their atomically granular structure gives rise to macroscopically measurable mismatch between devices. Industry now recognises that such variations represent a major challenge to the scaling and integration of current and future CMOS circuits. In order to counteract the deleterious effects of variability in future technology generations, revolutionary changes will need to be made in the way that devices, circuits and systems are designed.

Fig. 1 Inset: device structure of minimal width 35 nm nMOSFET showing the effect of random discrete dopants in channel, source and drain on the potential distribution. Graph: subthreshold characteristics for an ensemble of 200 such nMOSFETs.	Fig. 2 Static noise margin distributions for sets of 200 SRAM cells, constructed from members of a large device ensemble. Predictive simulation of 25, 18 and 13 nm gate length devices has been carried out to form the ensembles, and static noise margins are calculated for six- and eight-transistor SRAM cells.

Fig. 1 illustrates the underlying problem, showing one source of variability (random discrete dopants) and its effect on the ID-VG characteristics of an ensemble of devices. Device simulation turns from a 3D to 4D problem, with the fourth dimension the ensemble size. Fig. 2 shows the results of Monte Carlo circuit analysis of SRAM cells at various levels of scaling, based on predictive device simulation. The computational effort involved in: performing such device simulations, extracting accurate SPICE models for future circuit simulation, and performing the Monte Carlo circuit simulations themselves, is prohibitive even for ensembles of the order of 100 members. However for accurate circuit yield analysis, tails in figures-of-merit curves out to 6σ-7σ must be calculated, implying ensembles of tens of millions of members. In this presentation we will review our solutions to the fundamental and practical problems of large scale statistical device and circuit simulation. We describe e-Science Grid technologies to exploit available computing power and deal with the large data sets resulting from statistical simulation, optimised device simulation based on an understanding of underlying device physics, and statistical enhancement techniques for circuit and system analysis.