ESSDERC/ESSCIRC Workshop
cmos variability research in europe: from atomic scale to circuits and systems
Edinburgh International Conference Centre
19th September 2008
19th September 2008
Reliable and variability-tolerant system on a chip design strategies
In this talk we address the need for a new family of runtime countermeasures against variability and degradation effects in CMOS electronic circuits and SoC. Although the concept is very promising, the acceptance by industry is still hindered by the lack of standardization efforts. New design strategies and standards are required, involving innovative design strategies for the digital functionality (e.g. accurate measurements of temperature, supply voltage (IR) drop, slack and time delay of a circuit parts, etc). Moreover, the higher levels of abstraction of the design are also affected, bringing into (re)consideration new aspects such as the new optimization methods for circuit topologies, the potential disruption of well established design flows (e.g., RTL to GDSII synthesis), interfacing protocols, and even software aspects. In essence a new paradigm shift will be required for the design of resilient systems under unreliable technologies.
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