ESSDERC/ESSCIRC Workshop
cmos variability research in europe: from atomic scale to circuits and systems

Figure 1: Top: Comparison of the experimental (open symbols) and predicted (plain lines) normalized mismatch in the drain current versus gate overdrive, for n-type and p-type FinFETs. Bottom: Error between the experimental and modeled ID mismatch.

As Moore’s law is leading the CMOS technology into the decananometer regime, the behavior of the MOSFET deviates from that of an ideal switch. The SCEs are the main source of this deviation, resulting in an increasingly difficult control over the scaled channels. Besides the SCEs, variations in various process parameters and their fluctuations also become higher as the channel area shrinks. These give rise to variability and mismatch in the transistor characteristics, affecting both the product performance and yield. The introduction of alternative multiple gate transistor architectures, such as SOI FinFET, can significantly improve transistor performance by a stronger coupling to the channel, and lower channel doping. Measurements and modeling of the mismatch in drain current, threshold voltage, and current factor between FinFET pairs are presented and developed for most advanced technology options [1-3]. An overview comparing FinFET performances with state of the art technologies and the ITRS is given. Furthermore, extracted mismatch parameters are used to assessing the impact of mismatch on FinFET circuit design for both analog and SRAM applications.