ESSDERC/ESSCIRC Workshop
cmos variability research in europe: from atomic scale to circuits and systems

Edinburgh International Conference Centre
19th September 2008

Variability in novel device architectures


Giuseppe Iannaccone

The focus of the activity in the NANOSIL NoE oriented in the “More Moore” direction is represented by devices for the 22 nm and 16 nm CMOS technology node. Such devices are characterized by an ultrathin body structure, for which options are evaluated for using double or triple gates, high-κ dielectrics and metal gates. Statistical variability affects all electrical parameters, and is partly due to unavoidable causes, related to the granularity of charge and matter, and to manufacturing limitations, which are particularly significant when CMOS technology abandons planar devices for truly 3D structures. Ultrathin body and multigate structures represent a very promising option also from the variability point of view, because their electrical characteristics are more robust with respect to geometrical and process variations. On the other hand, the less mature technology and the more complex structures might imply a lesser control of geometry and doping. Full understanding of the relative impact of these factors requires:
  • experiments dedicated to statistical electrical and morphological characterization;
  • detailed statistical modelling capable of taking into account the granularity of matter and the tolerances of the CMOS process;
  • the derivation of analytical models of the sensitivity of the electrical parameters to geometry and process parameters, and of their distribution.
The talk will present the coordinated activity on such aspects in the Nanosil NoE, the lessons learned and the main issues still ahead.
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