ESSDERC/ESSCIRC Workshop
cmos variability research in europe: from atomic scale to circuits and systems

Building transistors with excellent average electrical performances is not enough for making a technological node industrially successful. Indeed the spread of such performances can act as a strong break on design performance and yield. Although this problem is not new, it is quite recent that it entered the digital applications’ world, for instance affecting SRAM memories. This is a direct consequence of transistors scaling. Indeed, as transistors get smaller they are more impacted by technological parameters’ fluctuations. In order to keep scaling engineers have to both reduce the processes spread and to build transistors that are more robust to such process fluctuations. In this context, it is mandatory to understand what the electrical fluctuations sources are and how they physically act on the transistor electrical behavior. Thought it is shown that transistor environment has to be taken care of since it can act as an external source of electrical fluctuations the bigger part of electrical fluctuations sources is internal to the transistor. The gate is a big contributor because it is made from granular materials and because it is affected by line edge roughness. The channel may be a strong or a low contributor depending on its engineering. Particularly, the pocket induced extra fluctuations can drastically affect bulk long transistors. The work which is presented is dedicated to this identification of variability sources for the 45 nm technological node. In particular and for the first time experimental measurement and atomistic were led on the same nominal device in order to quantify each of the main variability sources which are the Line Edge Roughness, the Poly Gate Granularity and the Random Discrete Dopant in the channel (Figure 1).

Figure 1: Random Discrete Dopant, Line Edge Roughness and Poly Grain Granularity induced threshold voltage fluctuations on a 45nm node nominal device.

During this presentation, first all of the test structures, the measurements procedures and the data treatment chain that were built in order to accurately extract electrical fluctuations will be shown. Then the device calibration and the atomistic simulations that were run to individually quantify variability sources will be detailed. The results obtained for each of the contributors will be shown and discussed. In particular, the difference that is commonly observed between NMOS and PMOS devices will be explained thanks to the Poly Gate Granularity contribution. The levels of variability will be benchmarked to the results experimentally obtained on devices made from innovative materials and architectures such as FD-SOI, FinFet and Gate All Around transistors.