ESSDERC/ESSCIRC Workshop
cmos variability research in europe: from atomic scale to circuits and systems

Edinburgh International Conference Centre
19th September 2008

Overview


The increasing variability in CMOS transistor characteristics has become a major challenge to scaling and integration. Statistical variability related to the fundamental discreteness of charge and matter, which cannot be eliminated by tighter process control, is becoming the major component of CMOS variability. The increasing device variability demands fundamental changes in the way that future integrated circuits and systems are designed. Strong links must be established between circuit design, system design and fundamental device technology to allow circuits and systems to accommodate the individual behaviour of every transistor on a chip. Design paradigms must change to accommodate the increasing variability.

This Workshop presents the status of CMOS variability related research in Europe conducted in three European and two national projects including:

NANOSIL: Silicon-based nanostructures and nanodevices for long term nanoelectronics applications (EU FP7)
PULLNANO: Pulling the limits of nanoCMOS Electronics (EU FP6)
REALITY: Reliable and variability tolerant system-on-a-chip design in More-Moore technologies (EU FP7)
NanoCMOS: Meeting the design challenges of nanoCMOS electronics (UK EPSRC)
NanoMat: Meeting the material challenges of nanoCMOS electronics (UK EPSRC)

The workshop covers a broad range of technology, devices, design aspects of the CMOS variability from atomic scale to circuit and system level.

The Keynote Speaker, Professor Toshiro Hiramoto from Tokyo University, will introduce the subject and will present the concerted research effort, supported by the MIRAI Project in Japan, in characterising and understanding the sources of statistical CMOS variability.

Last Updated July 07 2008.

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