DATE 2009

Workshop on Process Variability:

New Techniques for the Design and Test of Nanoscale Electronics

This workshop, organised by Dr Pete Sedcole of Imperial College, and nanoCMOS members Dr Scott Roy and Prof Mark Zwolinski, provided a forum for researchers from industry and academia to exchange ideas and present the latest results on different approaches to dealing with variability in devices and sytems at the 45nm technology and below. Please click on the title of the talk to download a PDF of the presentation slides, if available.

Session 1
 “A global approach, from device to system, to address variabilities in advanced technologies”
Marc Belleville, CEA / LETI-MINATEC, FR

“Multi-Level Simulation of Process Variability for Systems Design”
Mark Zwolinski, University of Southampton, UK

Session 2
“Surviving Process Variations with Adaptive Techniques”
Philippe Royannez, Texas Instruments, FR

“Improving Design Margins with Statistical Methods”
Vassilios Gerousis, Cadence, US

Session 3
“Recent advances (from Munich) in dealing with process variations”
Ulf Schlichtmann, Technical University Munich, DE

“Influence of process variability on design, test and debugging of multi-step ADCs”
Amir Zjajo, NXP, NL (TBC)

Session 4
“Process Variation of Emerging Devices: Case Studies on Carbon Nanotube (CNT)-based Devices” Shinobu Fujita, Toshiba, JP