Welcome

Welcome to the website of the nano-CMOS project. This site is currently under construction, but it is hoped that it will contain news and information about the progress of the nano-CMOS project as well as the opportunity to get in touch with the partner members of this project.

News

DATE Workshop Presentations Available
The slides from a number of the talks at the 2009 DATE Conference Workshop on Process Variability: New Techniques for the Design and Test of Nanoscale Electronics are now available here

Upcoming Event: 12th and 13th of May 2009
International Conference on CMOS Variability
We are happy to announce that the second International Conference on CMOS Variability (ICCV2): "Living With Variability" will take place in London this May. Please visit the National Micro-electronics Institute web page to see the programme and registration information.

ESSDERC Workshop Presentations Available
The slides from all of the talks at the recent ESSDERC Workshop on CMOS variability workshop are now available for download on the workshop webpage.

New Webpage Section - 23 September 2008
We have added a new section to the webpage with some presentations given by some of the project partners at a recent meeting.

Upcoming Event: 19th September 2008
ESSDERC/ESSCERC Workshop - CMOS Variability Research in Europe: "From Atomic Scale to Circuits and Systems"
Covering a broad range of technology, devices and design aspects of CMOS variability from atomic scale to circuit and system level, this workshop presents current, state of the art, CMOS variability research from 3 European and 2 UK projects including NANOSIL, PULLNANO, REALITY, NanoCMOS and NanoMAT.

Upcoming Event: 23rd October 2007
International Conference on CMOS Variability: "The Impact of Variability on Design." The National Microelectronics Institute (NMI) in collaboration with the NanoCMOS project is providing a unique oppurtunity for system, chip and device designers, technology developers, EDA suppliers and wafer foundries to gain crucial insight from recognised world experts.

Upcoming Event: 24rd October 2007
1st Annual NanoCMOS Review Meeting The 1st public review of the Uk eScience pilot project - "Meeting the Design Challenges of NanoCMOS electronics".

About

The UK Engineering and Physical Sciences Research Council (EPSRC) in collaboration with leading design houses, chip manufacturers and ECAD vendors has given funding of £5.3M ($9.1M) to apply e-Science and Grid technology to tackle some of the fundamental challenges facing nano-CMOS design.

Progressive scaling of CMOS transistors, as tracked by the International Technology Roadmap for Semiconductors (ITRS) and captured in Moore’s law, has driven the phenomenal success of the semiconductor industry, delivering larger, faster and, cheaper circuits. Silicon technology has now entered the nano-CMOS era with 40 nm MOSFETs already in mass production and sub-10 nm transistors scheduled for production by 2018.

However the years of ‘happy scaling’ are over and the fundamental challenges that the semiconductor industry faces, at both technology and device level, will impinge deeply upon the design of future integrated circuits and systems. It is widely recognised that variability in device characteristics and the need to introduce novel device architectures both represent major challenges to scaling and integration for present and next generation nano-CMOS transistors and circuits. The rapid increase in intrinsic parameter fluctuations stemming from the fundamental discreteness of charge and matter and their statistical impact on device behaviour is a major source of device variability. The intrinsic parameter fluctuations are fundamental, truly stochastic and cannot be eliminated by tighter process control.

Fig.1a Fig.1b Fig.1b
Random discrete dopants and line edge roughness in a 35 nm MOSFET representative for the transistors that are in mass production now. Corresponding variations in the current-voltage characteristics of 200 transistors with different dopant distributions. Corresponding distribution of the static noise margins in 6T SRAM cells.

The increasing device variability demands revolutionary changes in the way that future integrated circuits and systems are designed. Strong links must be established between circuit design, system design and fundamental device technology to allow circuits and systems to accommodate the individual behaviour of every transistor on a chip. Design paradigms must change to accommodate the increasing variability. Adjusting for new device architectures and device variability will add significant complexity to the design process, requiring the orchestration of a broad spectrum of design tools by geographically distributed teams of device experts, circuit and system designers. This can only be achieved by embedding e-Science technology and know-how across the whole nano-CMOS electronics design process and revolutionising the way in which these disparate groups currently work.